2.6.4
Power-Down State
The power-down state includes three modes: sleep mode, software standby mode, and hardware
standby mode.
Sleep Mode: Is entered when a SLEEP instruction is executed. The CPU halts, but CPU register
contents remain unchanged and the on-chip supporting modules continue to function.
Software Standby Mode: Is entered if the SLEEP instruction is executed while the SSBY
(Software Standby) bit in the system control register (SYSCR) is set. The CPU and all on-chip
supporting modules halt. The on-chip supporting modules are initialized, but the contents of the
on-chip RAM and CPU registers remain unchanged as long as a specified voltage is supplied. I/O
port outputs also remain unchanged.
Hardware Standby Mode: Is entered when the input at the STBY pin goes low. All chip
functions halt, including I/O port output. The on-chip supporting modules are initialized, but on-
chip RAM contents are held.
See section 22, Power-Down State, for further information.
2.7
Access Timing and Bus Cycle
The CPU is driven by the system clock (ø). The period from one rising edge of the system clock to
the next is referred to as a “state.” Memory access is performed in a two- or three-state bus cycle.
On-chip memory, on-chip supporting modules, and external devices are accessed in different bus
cycles as described below.
2.7.1
Access to On-Chip Memory (RAM and ROM)
On-chip ROM and RAM are accessed in a cycle of two states designated T1 and T2. Either byte or
word data can be accessed, via a 16-bit data bus. Figure 2.13 shows the on-chip memory access
cycle. Figure 2.14 shows the associated pin states.
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HITACHI [ HITACHI SEMICONDUCTOR ]
