Before Execution of BCLR Instruction
P47
Input
Low
0
P46
Input
High
0
P45
Output
Low
1
P44
Output
Low
1
P43
Output
Low
1
P42
Output
Low
1
P41
Output
Low
1
P40
Output
Low
1
Input/output
Pin state
DDR
DR
1
0
0
0
0
0
0
0
Execution of BCLR Instruction
BCLR #0, @P4DDR ; clear bit 0 in data direction register
After Execution of BCLR Instruction
P47
Output
Low
1
P46
Output
High
1
P45
Output
Low
1
P44
Output
Low
1
P43
Output
Low
1
P42
Output
Low
1
P41
Output
Low
1
P40
Input
High
0
Input/output
Pin state
DDR
DR
1
0
0
0
0
0
0
0
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR
are set to 1, making P47 and P46 output pins.
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HITACHI [ HITACHI SEMICONDUCTOR ]
