Table 1.1 Features
Item
Specification
CPU
Two-way general register configuration
•
•
Eight 16-bit registers, or
Sixteen 8-bit registers
High-speed operation
•
Maximum clock rate (ø clock): 16 MHz at 5 V, 12 MHz at 4 V or 10 MHz
at 3 V
•
8- or 16-bit register-register add/subtract: 125 ns (16 MHz), 167 ns
(12 MHz), 200 ns (10 MHz)
•
•
8 × 8-bit multiply: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz)
16 ÷ 8-bit divide: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz)
Streamlined, concise instruction set
•
•
•
Instruction length: 2 or 4 bytes
Register-register arithmetic and logic operations
MOV instruction for data transfer between registers and memory
Instruction set features
•
•
•
•
Multiply instruction (8 bits × 8 bits)
Divide instruction (16 bits ÷ 8 bits)
Bit-accumulator instructions
Register-indirect specification of bit positions
Memory
•
•
•
H8/3437: 60-kbyte ROM; 2-kbyte RAM
H8/3436: 48-kbyte ROM; 2-kbyte RAM
H8/3434: 32-kbyte ROM; 1-kbyte RAM
16-bit free-running
timer (1 channel)
•
•
•
One 16-bit free-running counter (can also count external events)
Two output-compare lines
Four input capture lines (can be buffered)
8-bit timer
Each channel has
(2 channels)
•
•
One 8-bit up-counter (can also count external events)
Two time constant registers
PWM timer
(2 channels)
•
•
Duty cycle can be set from 0 to 100%
Resolution: 1/250
Watchdog timer
(WDT) (1 channel)
•
•
Overflow can generate a reset or NMI interrupt
Also usable as interval timer
2
HITACHI [ HITACHI SEMICONDUCTOR ]
