11.4
Application Notes
11.4.1 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T3 state of a write cycle to the timer counter,
the write takes priority and the timer counter is not incremented. See figure 11.7.
Write cycle (CPU writes to TCNT)
T1
T2
T3
ø
TCNT address
Internal address bus
Internal write signal
TCNT clock pulse
TCNT
N
M
Counter write data
Figure 11.7 TCNT Write-Increment Contention
11.4.2 Changing the Clock Select Bits (CKS2 to CKS0)
Software should stop the watchdog timer (by clearing the TME bit to 0) before changing the value
of the clock select bits. If the clock select bits are modified while the watchdog timer is running,
the timer count may be incremented incorrectly.
11.4.3 Recovery from Software Standby Mode
TCSR bits, except bits 0–2, and the TCNT counter are reset when the chip recovers from software
standby mode. Re-initialize the watchdog timer as necessary to resume normal operation.
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HITACHI [ HITACHI SEMICONDUCTOR ]
