13.1.3 Input/Output Pins.................................................................................................. 286
13.1.4 Register Configuration.......................................................................................... 286
13.2 Register Descriptions ......................................................................................................... 287
13.2.1 I2C Bus Data Register (ICDR).............................................................................. 287
13.2.2 Slave Address Register (SAR).............................................................................. 287
13.2.3 I2C Bus Mode Register (ICMR)............................................................................ 288
13.2.4 I2C Bus Control Register (ICCR).......................................................................... 289
13.2.5 I2C Bus Status Register (ICSR) ............................................................................ 292
13.2.6 Serial/Timer Control Register (STCR)................................................................. 296
13.3 Operation............................................................................................................................ 297
13.3.1 I2C Bus Data Format............................................................................................. 297
13.3.2 Master Transmit Operation................................................................................... 298
13.3.3 Master Receive Operation .................................................................................... 300
13.3.4 Slave Transmit Operation ..................................................................................... 302
13.3.5 Slave Receive Operation....................................................................................... 304
13.3.6 IRIC Set Timing and SCL Control ....................................................................... 305
13.3.7 Noise Canceler...................................................................................................... 306
13.3.8 Sample Flowcharts................................................................................................ 307
13.4 Application Notes .............................................................................................................. 311
Section 14 Host Interface................................................................................................... 317
14.1 Overview............................................................................................................................ 317
14.1.1 Block Diagram...................................................................................................... 318
14.1.2 Input and Output Pins ........................................................................................... 319
14.1.3 Register Configuration.......................................................................................... 320
14.2 Register Descriptions ......................................................................................................... 321
14.2.1 System Control Register (SYSCR)....................................................................... 321
14.2.2 Host Interface Control Register (HICR)............................................................... 321
14.2.3 Input Data Register 1 (IDR1)................................................................................ 322
14.2.4 Output Data Register 1 (ODR1) ........................................................................... 323
14.2.5 Status Register 1 (STR1) ...................................................................................... 323
14.2.6 Input Data Register 2 (IDR2)................................................................................ 324
14.2.7 Output Data Register 2 (ODR2) ........................................................................... 325
14.2.8 Status Register 2 (STR2)...................................................................................... 325
14.2.9 Serial/Timer Control Register (STCR)................................................................. 327
14.3 Operation............................................................................................................................ 328
14.3.1 Host Interface Operation....................................................................................... 328
14.3.2 Control States........................................................................................................ 328
14.3.3 A20 Gate................................................................................................................. 329
14.4 Interrupts............................................................................................................................ 332
14.4.1 IBF1, IBF2............................................................................................................ 332
14.4.2 HIRQ11, HIRQ1, and HIRQ12................................................................................. 332
14.5 Application Note................................................................................................................ 333
vii
HITACHI [ HITACHI SEMICONDUCTOR ]
