64CH Common Driver For Dot Matrix LCD 10
Data Delay Time
FRM Delay Time
M Delay Time
tD
tDF
tDM
tWLC
tWHC
tWL1
tWL2
tWH1
tWH2
5
-2
-2
35
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
-
-
-
-
-
µs
CL2 Low Level Width
CL2 High Level Width
CLK1 Low Level Width
CLK2 Low Level Width
CLK1 High Level Width
CLK2 High Level Width
CLK1-CLK2 Phase Difference tD12
CLK2-CLK1 Phase Difference tD21
CLK1,CLK2 Rise/Fall Time
35
700
700
2100
2100
700
700
-
ns
-
-
-
tR/t F
150
Slave mode (MS=VSS)
CL2
tWLC1
tF
tR
(PLK2=VSS)
0.7VDD
0.3VDD
tWHC1
tWLC
tWLC2
tSU
CL2
(PLK2=VDD)
tF
tR
tD
tHCL
DIO1(SHL=VDD)
DIO2(SHL=VSS)
Input Data
0.7VDD
0.3VDD
tH
DIO1(SHL=VDD)
DIO2(SHL=VSS)
Output Data
0.7VDD
0.3VDD
CHARACTERISTICS
CL2 Low Level Width
CL2 High Level Width
CL2 Low Level Width
CL2 High Level Width
Data Setup Time
SYMBOL
tWLC1
tWHC1
tWLC2
tWHL
tSU
tDH
tD
tH
tR/tF
MIN
450
150
150
450
100
100
-
TYP
MAX
-
-
-
-
-
-
200
-
30
UNIT
NOTE
-
-
-
-
-
-
-
-
-
PCLK2=VSS
PCLK2=VSS
PCLK2=VDD
PCLK2=VDD
ns
Data Hold Time
Data Delay Time
*1
Output Data Hold Time
CL2 Rise/Fall Time
*1: Connect load CL=30pF
10
-
OUTPUT
30pF
HB [ HB ELECTRONIC COMPONENTS ]
