82C37A
Current Word Count Register - Each channel has a 16-bit Mode Register - Each channel has a 6-bit Mode register
Current Word Count register. This register determines the associated with it. When the register is being written to by
number of transfers to be performed. The actual number of the microprocessor in the Program condition, bits 0 and 1
transfers will be one more than the number programmed in determine which channel Mode register is to be written.
the Current Word Count register (i.e., programming a count When the processor reads a Mode register, bits 0 and 1 will
of 100 will result in 101 transfers). The word count is both be ones. See the following diagram and Figure 4 for
decremented after each transfer. When the value in the Mode register functions and addresses.
register goes from zero to FFFFH, a TC will be generated.
This register is loaded or read in successive 8-bit bytes by
Mode Register
the microprocessor in the Program Condition. See Figure 6
for programming information. Following the end of a DMA
service it may also be reinitialized by an Autoinitialization
back to its original value. Autoinitialization can occur only
when an EOP occurs. If it is not Autoinitialized, this register
will have a count of FFFFH after TC.
7
6
5
4
3
2
1
0
BIT NUMBER
00 Channel 0 select
01 Channel 1 select
10 Channel 2 select
11 Channel 3 select
XX Readback
Base Address and Base Word Count Registers - Each
channel has a pair of Base Address and Base Word Count
registers. These 16-bit registers store the original value of
their associated current registers. During Autoinitialize these
values are used to restore the current registers to their
original values. The base registers are written simulta-
neously with their corresponding current register in 8-bit
bytes in the Program Condition by the microprocessor. See
Figure 6 for programming information. These registers can-
not be read by the microprocessor.
00 Verify transfer
01 Write transfer
10 Read transfer
11 Illegal
XX If bits 6 and 7 = 11
0
1
Autoinitialization disable
Autoinitialization enable
0
1
Address increment select
Address decrement select
Command Register - This 8-bit register controls the opera-
tion of the 82C37A. It is programmed by the microprocessor
and is cleared by RESET or a Master Clear instruction. The
following diagram lists the function of the Command register
bits. See Figure 4 for Read and Write addresses.
00 Demand mode select
01 Single mode select
10 Block mode select
11 Cascade mode select
Command Register
Request Register - The 82C37A can respond to requests
for DMA service which are initiated by software as well as by
a DREQ. Each channel has a request bit associated with it in
the 4-bit Request register. These are non-maskable and
subject to prioritization by the Priority Encoder network.
Each register bit is set or reset separately under software
control. The entire register is cleared by a Reset or Master
Clear instruction. To set or reset a bit, the software loads the
proper form of the data word. See Figure 4 for register
address coding, and the following diagram for Request
register format. A software request for DMA operation can
be made in block or single modes. For memory-to-memory
transfers, the software request for channel 0 should be set.
When reading the Request register, bits 4-7 will always read
as ones, and bits 0-3 will display the request bits of channels
0-3 respectively.
7
6
5
4
3
2
1
0
BIT NUMBER
0
1
Memory-to-memory disable
Memory-to-memory enable
0
1
X
Channel 0 address hold disable
Channel 0 address hold enable
If bit 0 = 0
0
1
Controller enable
Controller disable
0
1
X
Normal timing
Compressed timing
If bit 0 = 1
0
1
Fixed priority
Rotating priority
Request Register
7
6
5
4
3
2
1
0
BIT NUMBER
0
1
X
Late write selection
Extended write selection
If bit 3 = 1
00 Select Channel 0
01 Select Channel 1
10 Select Channel 2
11 Select Channel 3
Don’t Care,
Write
Bits 4-7
All Ones,
Read
0
1
DREQ sense active high
DREQ sense active low
0
1
Reset request bit
Set request bit
0
1
DACK sense active low
DACK sense active high
4-200
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