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MR82C37A-12/B 参数 Datasheet PDF下载

MR82C37A-12/B图片预览
型号: MR82C37A-12/B
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS高性能可编程DMA控制器 [CMOS High Performance Programmable DMA Controller]
分类和应用: 外围集成电路控制器时钟
文件页数/大小: 23 页 / 207 K
品牌: HARRIS [ HARRIS CORPORATION ]
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82C37A  
o
o
AC Electrical Specifications  
V
= +5.0V ±10%, GND = 0V, T = 0 C to +70 C (C82C37A),  
A
CC  
o
o
T = -40 C to +85 C (I82C37A),  
A
o
o
T = -55 C to +125 C (M82C37A)  
A
82C37A-5  
82C37A  
82C37A-12  
SYMBOL  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
DMA (MASTER) MODE  
(1)TAEL  
(2)TAET  
(3)TAFAB  
(4)TAFC  
(5)TAFDB  
AEN HIGH from CLK LOW (S1) Delay  
Time  
-
-
-
-
-
175  
130  
90  
-
-
-
-
-
105  
80  
-
-
-
-
-
50  
50  
55  
50  
90  
ns  
ns  
ns  
ns  
ns  
AEN LOW from CLK HIGH (SI) Delay  
Time  
ADR Active to Float Delay from CLK  
HIGH  
55  
READ or WRITE Float Delay from  
CLK HIGH  
120  
170  
75  
DB Active to Float Delay from CLK  
HIGH  
135  
(6)TAHR  
(7)TAHS  
(8)TAHW  
(9)TAK  
ADR from READ HIGH Hold Time  
DB from ADSTB LOW Hold Time  
ADR from WRITE HIGH Hold Time  
TCY-100  
TCL-18  
TCY-65  
-
-
TCY-75  
TCL-18  
TCY-65  
-
-
TCY-65  
TCL-18  
TCY-50  
-
-
-
ns  
ns  
ns  
ns  
-
-
-
-
-
DACK Valid from CLK LOW  
Delay Time  
170  
105  
69  
EOP HIGH from CLK HIGH  
Delay Time  
-
-
170  
100  
-
-
105  
60  
-
-
90  
35  
ns  
ns  
EOP LOW from CLK HIGH  
Delay Time  
(10)TASM  
(11)TASS  
(12)TCH  
(13)TCL  
ADR Stable from CLK HIGH  
DB to ADSTB LOW Setup Time  
CLK HIGH Time (Transitions 10ns)  
CLK LOW Time (Transitions 10ns)  
CLK Cycle Time  
-
TCH-20  
70  
110  
-
TCH-20  
55  
60  
-
50  
ns  
ns  
ns  
ns  
ns  
ns  
-
-
TCH-20  
-
-
-
30  
30  
80  
-
-
50  
-
-
43  
-
-
-
-
(14)TCY  
(15)TDCL  
200  
-
125  
-
CLK HIGH to READ or WRITE LOW  
Delay  
190  
130  
120  
(16)TDCTR  
(17)TDCTW  
(18)TDQ  
READ HIGH from CLK HIGH (S4)  
Delay Time  
-
-
-
190  
130  
120  
-
-
-
115  
80  
-
-
-
80  
70  
30  
ns  
ns  
ns  
WRITE HIGH from CLK HIGH (S4)  
Delay Time  
HRQ Valid from CLK HIGH  
Delay Time  
75  
(19)TEPH  
(20)TEPS  
EOP Hold Time from CLK LOW (S2)  
EOP LOW to CLK LOW Setup Time  
90  
40  
-
-
90  
25  
-
-
50  
0
-
-
ns  
ns  
4-206  
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