82C55A
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
INTRA
PC3
1
1
1/0 1/0 1/0
PA7-PA0
PC7
8
OBFA
ACKA
INTE
PC6
PC2-PC0
1 = INPUT
0 = OUTPUT
1
INTE
2
STBA
IBFA
PC4
PC5
PORT B
1 = INPUT
0 = OUTPUT
WR
RD
GROUP B MODE
0 = MODE 0
1 = MODE 1
3
PC2-PC0
I/O
FIGURE 11. MODE CONTROL WORD
FIGURE 12. MODE 2
DATA FROM
CPU TO 82C55A
WR
tAOB
OBF
INTR
ACK
tWOB
tAK
tST
STB
IBF
tSIB
tPS
tAD
tKD
PERIPHERAL
BUS
tRIB
tPH
RD
DATA FROM
PERIPHERAL TO 82C55A
DATA FROM
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF • MASK • STB • RD ÷ OBF •
MASK • ACK • WR)
FIGURE 13. MODE 2 (BI-DIRECTIONAL)
11
HARRIS [ HARRIS CORPORATION ]
