HSP3824
Waveforms
tP
tL
tH
SCLK
tH1
tS1
SD, AS, R/W, CS
tD1
SD (AS OUTPUT)
R/W
SD
tE1
tF1
FIGURE 23. SERIAL CONTROL PORT SIGNAL TIMING
tCP
tCL
tCH
MCLK
TXCLK
tD2
tD2
TXRDY, I, Q
TXD
tS2
tH2
FIGURE 24. TX PORT SIGNAL TIMING
MCLK
RXCLK
MD_RDY
RXD
tD3
tD3
tD3
NOTE: RXD is output one MCLK after RXCLK rising to provide data hold time.
FIGURE 25. RX PORT SIGNAL TIMING
MCLK
tD4
TEST 0-7, AGC, CCA, ANTSEL, TEST_CK
FIGURE 26. MISCELLANEOUS SIGNAL TIMING
40