HSP3824
Reset
The RESET signal is used during the power down mode as The transmitter accepts data from the external source,
described in the Power Down Mode section. The RESET scrambles it, differentially encodes it as either DBPSK or
does not impact any of the internal configuration registers DQPSK, and mixes it with the BPSK PN spreading. The
when asserted. Reset does not set the device in a default baseband digital signals are then output to the external IF
configuration, the HSP3824 must always be programmed on modulator.
power up. The HSP3824 must be programmed with RESET
The transmitter includes a programmable PN generator that
inactive.
can provide 11, 13, 15 or 16 chip sequences. The transmitter
also contains a programmable clock divider circuit that
allows for various data rates. The master clock (MCLK) can
Transmitter Description
be a maximum of 44MHz.
The HSP3824 transmitter is designed as a Direct Sequence
Spread Spectrum DBPSK/DQPSK modulator. It can handle
data rates of up to 4 MBPS (refer to AC and DC specifica-
tions). The major functional blocks of the transmitter include
a network processor interface, DBPSK/DQPSK modulator, a
data scrambler and a PN generator, as shown on Figure 9.
The chip rates are programmed through CR3 for TX and
CR2 for RX. In addition the data rate is a function of the
sample clock rate (MCLK) and the number of PN bits per
symbol.
The following equations show the Symbol rate for both TX
and RX as a function of MCLK, Chips per symbol and N.
The transmitter has the capability to either generate its own
synchronization preamble and header or accept the pream-
ble and header information from an external source. In the
first case, the transmitter knows when to make the DBPSK
to DQPSK switchover, as required.
N is a programmable parameter through configuration regis-
ters CR 2and CR 3. The value of N is 2, 4, 8 or 16. N is used
internally to divide the MCLK to generate other required
clocks for proper operation of the device.
The preamble and header are always transmitted as DBPSK
waveforms while the data packets can be configured to be
either DBPSK or DQPSK. The preamble is used by the
receiver to achieve initial PN synchronization while the
header includes the necessary data fields of the communi-
cations protocol to establish the physical layer link. There is
a choice of four potential preamble/header formats that the
HSP3824 can generate internally. These formats are
referred to as mode 0, 1, 2 and 3. Mode 0 uses the minimum
number of available header fields while mode 3 is a full pro-
tocol mode utilizing all available header fields. The number
of the synchronization preamble bits is programmable.
Symbol Rate = MCLK/(N x Chips per Symbol).
The bit rate Table 7 shows examples of the relationships
expressed on the symbol rate equation.
The modulator is capable of switching rate automatically in
the case where the preamble and header information are
DBPSK modulated, and the data is DQPSK modulated.
The modulator is completely independent from the demodu-
lator, allowing the PRISM baseband processor to be used in
full duplex operation.
PROCESSOR
INTERFACE
CONTROL PORT
TX_I_OUT
IOUT
DBPSK/DQPSK
DIFFERENTIAL ENCODER
TX_Q_OUT
SPREADER
QOUT
PACKET
FORMAT/
CRC-16
TX PORT
TX_SCRAM_SEED
7
TX_DATA
SHIFT REG
7
TX_SPREAD_STQ
TX_BIT_CK
16
SCRAM_TAPS
TX_CHIP_CK
7
7
SHIFT REG
SCRAMBLER
PN GENERATOR
FIGURE 9. MODULATOR DIAGRAM
14
HARRIS [ HARRIS CORPORATION ]
