HMP8112
ming registers. The DC RESTORE pulse can be pro-
grammed with the DC RESTORE Start and End time control
registers. DC RESTORE should be asserted 6.5µs after the
Introduction
The HMP8112 is an NTSC/PAL compatible Video Decoder
with both chroma burst and line locked digital phase locked
loops. The HMP8112 contains two 8-bit A/D converters and
falling edge of horizontal sync (0
) and held for a dura-
HSYNC
tion of 2µs. Both HAGC and DC RESTORE are synchronous
to the output sample rate (OSR) converter and are clocked
in OSR (pixel clock) clock periods. The OSR clock rate is
dependent on the input standard used. See Table 1 for the
2
an I C port for programming internal registers.
Analog Video/Mux Inputs
The Luminance channel has three analog video inputs that register values used for the different video standards.
can be used for composite or the Y input of a S-Video signal,
TABLE 1. HAGC AND DC RESTORE VALUES
and one analog input for chrominance. LIN2 is used with CIN
to interface an S-Video input. Three composite or two com-
posite and one S-Video inputs can be applied to the
HMP8112 at any one time. Control of the analog front end is
selected by bits 2 and 1 of the Video Input Control Register.
DC
RESTORE
START/END START/END START/END
VIDEO
OUTPUT
STANDARD
HAGC
HSYNC
VALUES
VALUES
VALUES
Square Pixel
NTSC
02F8/0008
0028/0040
0020/0050
H
H
H
Anti-Aliasing Filter
640x480
An external anti-alias filter is required to achieve optimum
performance and prevent high frequency components from
being aliased back into the video image. For the LIN inputs a
single filter is connected to L_OUT and L_ADIN. For CIN the
anti-aliasing filter should be connected to the CIN input. A
recommended filter is shown below.
CCIR601 NTSC
720x480
033F/0000
033F/0000
0037/0052
0037/0052
033B/0060
033B/0060
H
H
H
H
CCIR601
PAL
720X512
H
H
Square Pixel
PAL
768X512
03A0/0018
0040/0054
0020/0070
82µH
H
H
H
680Ω
L_ADIN
(PIN 8)
L_OUT
(PIN 9)
15pF
5.62kΩ
15pF
White Peak Enable
AGND
The white peak enable input, (WPE) enables or disables the
white peak control. Enabled, (logic high) when the digital
outputs exceed code 248, the AGC will reduce the gain of
the video amplifier to prevent over-ranging the A/D. If dis-
abled, the AGC operates normally, keeping the horizontal
sync tip at code 0 and allowing the A/D’s range to go to 255
at the maximum peak input.
LOW PASS FILTER
1.0µF
CHROMA
IN
CIN
(PIN 19)
75Ω
NTSC/PAL Decoder
FIGURE 1. RECOMMENDED ANTI-ALIASING FILTER
AGC And Clamp Circuit
The NTSC/PAL decoder is designed to convert incoming
Composite or Separated (SVHS, Y/C) video into it’s YCbCr
component parts. The digital phase locked loops are
designed to synchronize to the various NTSC/PAL stan-
dards. They provide a stable internal 4xf
the Color Sub-Carrier) video clock for color demodulation,
and a line locked clock for vertical spatial pixel alignment.
Inputs LIN0-2 contain a sync tip AGC amplifier. During the
sync tip the value of the A/D is driven to code 0 by gaining up
the video input signal. The sync tip AGC is sampled during the
HAGC pulse time which is controlled by the HAGC Pulse Start
Time and End Time registers. The LIN0-2 inputs apply a DC
clamp reference to the back porch of the video. This is con-
trolled by the DC-RESTORE Pulse Start Time and End Time
Registers.
(Frequency of
SC
The decoder uses the CLK to run the A/D converters and the
phase locked loops. This asynchronous master clock for the
decoder eliminates the need for a unique clock source in a Mul-
timedia application. CLK can run from 20MHz to 30MHz when
using the 16-bit Synchronous Data output Mode. The user
must program the CLK to Color Sub-Carrier Ratio to match the
CLK frequency used (see Internal Phase Locked Loops discus-
sion). When using the 8-bit Burst Data Output Mode the CLK
should be a 24.5454MHz, 27MHz or 29.5MHz depending on
the output video standard chosen. The crystal oscillator must
have a ±50ppm accuracy and a 60/40% duty cycle symmetry to
ensure proper operation. Since the video data from the external
A/D’s are sampled at the CLK frequency a sample rate con-
verter is employed to convert the data from the CLK rate to the
After a RESET, a change of the video standard, or a PLL
Chrominance Subcarrier Ratio Register load, HAGC and DC
RESTORE are overlapped, until LOCKED is asserted. (the
PLL has acquired a stable line lock). This is the acquisition
mode of the PLL where the decoder is trying to lock to a new
video source. Once the PLL is LOCKED, HAGC and DC
RESTORE are moved out to the default programmed values
in the user programming registers. The HAGC should be set
coincident to the incoming horizontal sync signal. The HAGC
pulse should be set to a width of 2µs.
Once the PLL is locked the DC RESTORE signal is moved
out to the default programmed values in the user program-
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HARRIS [ HARRIS CORPORATION ]
