HMP8112
PCB Layout Considerations
A PCB board with a minimum of 4 layers is recommended, with quency power supply rejection.
layers 1 and 4 (top and bottom) for signals and layers 2 and 3
for power and ground. The PCB layout should implement the
lowest possible noise on the power and ground planes by pro-
Evaluation Boards
The HMP8112EVAL stand-alone evaluation board allows
viding excellent decoupling. PCB trace lengths between groups
of V and GND pins should be as short as possible.
connecting the NTSC/PAL decoder into an IBM PC ISA slot
for evaluation. The board contains the HMP8112 NTSC/PAL
decoder, 2 Mbytes of VRAM and a encoder. The board can
accept Composite or S-Video input and display video on a
stand composite or S-Video display. The ISA bus and evalu-
ation software allows easy plug and play of the decoder for
analysis with such tools as a VM700 video test system.
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The optimum layout places the HMP8112 as close as
possible to the power supply connector and the video output
connector.
Component Placement
External components should be positioned as close as pos-
sible to the appropriate pin, ideally such that traces can be
connected point to point. Chip capacitors are recommended
where possible, with radial lead ceramic capacitors the sec-
ond-best choice.
Power supply decoupling should be done using a 0.1µF
ceramic capacitor in parallel with a 0.01µF chip capacitor for
each group of V
pins to ground. These capacitors should
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be located as close to the V
using short, wide traces.
and GND pins as possible,
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Ground Plane
A common ground plane for all devices, including the
HMP8112, is recommended. All GND pins on the HMP8112
must be connected to the ground plane.
Power Planes
The HMP8112 should have its own power plane that is iso-
lated from the common power plane of the board, with a gap
between the two power planes of at least 1/8 inch. All V
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pins on the HMP8112 must be connected to this HMP8112
power plane. The HMP8112 power plane should be con-
nected to the board’s normal V
power plane at a single
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point though a low-resistance ferrite bead, such as a Ferrox-
cube 5659065-3B, Fair-Rite 2743001111, or TDK BF45-
4001. The ferrite bead provides resistance to switching cur-
rents, improving the performance of HMP8112. A single
47µF capacitor should also be used between the HMP8112
power plane and the ground plane to control low-frequency
power supply ripple.
If a separate linear regulator is used to provide power to the
HMP8112 power plane, the power-up sequence should be
designed to ensure latchup will not occur. A separate linear
regulator is recommended if the power supply noise on the
V
pins exceeds 200mV. About 10% of the noise (that is
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less than 1MHz) on the V
outputs.
pins will couple onto the analog
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Analog Signals
Traces containing digital signals should not be routed over,
under, or adjacent to the analog output traces to minimize
crosstalk. If this is not possible, coupling can be minimized
by routing the digital signals at a 90 degree angle to the ana-
log signals. The analog output traces should also not overlay
the HMP8112 and V
power planes to maximize high-fre-
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HARRIS [ HARRIS CORPORATION ]
