CD4049UB, CD4050B
Test Circuits
V
CC
INPUTS
INPUTS
V
IH
V
SS
V
CC
V
CC
OUTPUTS
+
DVM
-
V
IL
I
DD
V
SS
V
SS
NOTE: Test any one input with other inputs at V
CC
or V
SS
.
FIGURE 13. QUIESCENT DEVICE CURRENT TEST CIRCUIT
FIGURE 14. INPUT VOLTAGE TEST CIRCUIT
CMOS 10V LEVEL TO DTL/TTL 5V LEVEL
V
CC
= 5V
V
CC
INPUTS
V
CC
I
V
SS
V
SS
10V = V
IH
0 = V
IL
V
SS
OUTPUTS
COS/MOS
IN
CD4049
INPUTS
5V = V
OH
0 = V
OL
OUTPUT
TO DTL/TTL
NOTE: Measure inputs sequentially, to both V
CC
and V
SS
connect
all unused inputs to either V
CC
or V
SS
.
FIGURE 15. INPUT CURRENT TEST CIRCUIT
In Terminal - 3, 5, 7, 9, 11, or 14
Out Terminal - 2, 4, 6, 10, 12 or 15
V
CC
Terminal - 1
V
SS
Terminal - 8
FIGURE 16. LOGIC LEVEL CONVERSION APPLICATION
V
DD
0.1µF
500µF
I
10kHz,
100kHz, 1MHz
C
L
INCLUDES FIXTURE CAPACITANCE
FIGURE 17. DYNAMIC POWER DISSIPATION TEST CIRCUITS
7
CD4049UB
C
L
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
HARRIS [ HARRIS CORPORATION ]
