CD4049UB, CD4050B
Test Circuits
V
CC
V
CC
V
CC
INPUTS
INPUTS
OUTPUTS
V
IH
V
SS
+
DVM
-
V
IL
I
DD
V
SS
V
SS
NOTE: Test any one input with other inputs at V
or V
.
CC
SS
FIGURE 13. QUIESCENT DEVICE CURRENT TEST CIRCUIT
FIGURE 14. INPUT VOLTAGE TEST CIRCUIT
CMOS 10V LEVEL TO DTL/TTL 5V LEVEL
V
= 5V
CC
V
CC
COS/MOS
IN
OUTPUT
TO DTL/TTL
INPUTS
OUTPUTS
V
CC
CD4049
INPUTS
I
10V = V
5V = V
IH
OH
V
0 = V
IL
0 = V
OL
SS
V
SS
V
In Terminal - 3, 5, 7, 9, 11, or 14
Out Terminal - 2, 4, 6, 10, 12 or 15
SS
V
V
Terminal - 1
Terminal - 8
NOTE: Measure inputs sequentially, to both V
CC
and V connect
SS
CC
SS
all unused inputs to either V
or V .
CC
SS
FIGURE 16. LOGIC LEVEL CONVERSION APPLICATION
FIGURE 15. INPUT CURRENT TEST CIRCUIT
V
DD
0.1µF
I
500µF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
L
10kHz,
100kHz, 1MHz
C
INCLUDES FIXTURE CAPACITANCE
L
FIGURE 17. DYNAMIC POWER DISSIPATION TEST CIRCUITS
7
HARRIS [ HARRIS CORPORATION ]
