CD22402
o
o
Switching Electrical Specifications T = 25 C and C = 15pF. Typical Temperature Coefficient for All Values of V
= 0.3%/ C
A
L
DD
TEST
CONDITIONS
PARAMETER (NOTE 4)
SYMBOL
V
(V)
MIN
TYP
MAX
UNITS
DD
Output State Propagation Delay Time (50% to 50%)
Low-to-High Level
t
t
5
-
-
40
20
80
40
ns
ns
PLH
High-to-Low Level
10
PHL
Output State Transition Time (10% to 90%)
Low-to-High
t
t
5
10
-
-
-
-
45
30
5
90
60
-
ns
ns
pF
TLH
High-to-Low
THL
Input Capacitance (Per Input)
NOTE:
C
I
4. The characteristics given are defined for unbuffered gate in the CMOS process of the CD22402.
Logic Diagram
VERTICAL DRIVE (VERT. RESET
TO FIRST VERT. PULSE)
51pF
10K
10K
22
24
6
INTEGRATOR
10
20
R
S
Q
Q
+
GENLOCK OSC.
S
R
Q
Q
GENLOCK
SYNC
HOR.
DR
(NOTE 5)
21
1
1M
1N914
0.001µF
(NOTE 6)
23
2
CRYSTAL
32 TIMES
HORIZ.
1M
503.496kHz
HOR. PROCESS
BLANKING
CLOCK TO
COUNTERS
100pF
NOTES:
5. Pin 21 high when pin 20 is high (or open).
6. Pin 1 high inhibits clock.
FIGURE 1. DETAIL OF THE OSCILLATOR/GENLOCK PORTION OF THE CD22402
8-44
HARRIS [ HARRIS CORPORATION ]
