CD22354A, CD22357A
Electrical Specifications
PARAMETER
Hold Time from 3rd Period of Bit
Clock Low to Frame Sync
(FS
X
or FS
R
)
Minimum Width of the Frame
Sync Pulse (Low Level)
NOTE:
1. For short frame sync timing, FS
X
and FS
R
must go high while their respective bit clocks are high.
(Continued)
SYMBOL
t
HBFI
TEST CONDITIONS
Long Frame Sync Pulse
(from 3 to 8-Bit Clock Periods Long)
MIN
100
TYP
-
MAX
-
UNITS
ns
t
WFL
64K Bit/s Operating Mode
160
-
-
ns
Pin Descriptions
PIN NO.
1
2
3
4
5
SYMBOL
V-
GND
VF
R
O
V+
FS
R
D
R
BCLK
R
/CLK-
SEL
Negative power supply, V- = -5V
±5%.
Analog and digital ground. All signals referenced to this pin.
Analog output of RECEIVE FILTER.
Positive power supply, V+ = 5V
±5%.
Receive Frame Sync Pulse which enables BCLK
R
to shift PCM data into D
R
. FS
R
is an 8kHz PULSE
TRAIN.
Receive Data Input. PCM data is shifted into D
R
following the FS
R
leading edge.
The Receive Bit Clock, which shifts data into D
R
after the frame sync leading edge, may vary from 64kHz
to 2.048MHz. Alternatively, the leading edge may be a logic input which selects either 1.536MHz/
1.544MHz or 2.048MHz for Master Clock in synchronous mode and BCLK
X
is used for both transmit and
receive directions.
Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLK
X
,
but best performance is realized from synchronous operation. When this pin is continuously connected
low, MCLK
X
is selected for all internal timing. When this pin is continuously connected high, the device is
powered down.
Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLK
R
,
but best performance is realized from synchronous operation.
The Bit Clock which shifts out the PCM Data on D
X
. May vary from 64kHz to 2.048MHz, but must be syn-
chronous with MCLK
X.
The THREE-STATE PCM Data Output which is enabled by FS
X
.
Transmit Frame Sync Pulse input which enables BCLK
X
to shift out the data on D
X
. FS
X
is an 8kHz
PULSE TRAIN.
Open drain output which pulses low during the encoder time slot.
Transmit gain adjust.
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input amplifier.
DESCRIPTION
6
7
8
MCLK
R
/PDN
9
MCLK
X
BCLK
X
D
X
FS
X
TS
X
GS
X
VF
X
I-
VF
X
I+
10
11
12
13
14
15
16
4-171
HARRIS [ HARRIS CORPORATION ]
