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CA1391E 参数 Datasheet PDF下载

CA1391E图片预览
型号: CA1391E
PDF下载: 下载PDF文件 查看货源
内容描述: 电视的卧式处理器 [TV Horizontal Processors]
分类和应用: 电视
文件页数/大小: 4 页 / 53 K
品牌: HARRIS [ HARRIS CORPORATION ]
 浏览型号CA1391E的Datasheet PDF文件第1页浏览型号CA1391E的Datasheet PDF文件第2页浏览型号CA1391E的Datasheet PDF文件第3页  
CA1391, CA1394
Application Information
Circuit Operation
(See Schematic Diagram)
The CA1391 and CA1394 contain the oscillator, phase
detector, and predriver sections necessary for the television
horizontal oscillator and AFC loop.
The oscillator is an RC type with Terminal 7 used to control the
timing. If it is assumed that Q
7
is initially off, then an external
capacitor connected from Terminal 7 to ground charges through
an external resistance connected between Terminals 6 and 7. As
soon as the voltage at Terminal 7 exceeds the potential set at the
base of Q
8
by resistors R
11
and R
12
, Q
7
turns on, and Q
6
sup-
plies base current to Q
5
and Q
10
. Transistor Q
5
discharges the
capacitor through R
4
until the base bias of Q
7
falls below that of
Q
8
at which time, Q
7
turns off, and the cycle repeats.
The sawtooth generated at the base of Q
4
appears across R
3
and turns off Q
3
whenever the sawtooth voltage rises to a value
that exceeds the bias set at Terminal 8. By adjusting the poten-
tial at Terminal 8, the duty cycle at the pre-drive output (Termi-
nal 1) may be changed. The phase detector is isolated from the
remainder of the circuit by R
31
, Z
2
, Q
15
and Q
16
. The phase
detector consists of the comparator Q
22
and Q
23
, and the
gated current source Q
18
. Negative going sync pulses at Ter-
minal 3 turn off Q
17
, and the current division between Q
22
and
Q
23
is then determined by the phase relationship of the sync
and the sawtooth waveform at Terminal 4, which is derived from
the horizontal flyback pulse. If there is no phase difference
between the sync and sawtooth, equal currents flow in the col-
lectors of Q
22
and Q
23
during each half of the sync pulse
period. The current in Q
22
is turned around by current mirror
Q
20
and Q
21
so that there is no net output current at Terminal 5
for balanced conditions. When a phase offset occurs, current
flows either in or out of Terminal 5. In circuit applications, this
terminal is connected to Terminal 7 through an external low
pass filter, thereby controlling the oscillator.
Shunt regulation for the circuit is obtained by using a V
BE
and zener multiplier. Resistors R
13
and R
14
multiply the V
BE
of Q
11
, and the ratio of R
15
and R
16
multiplies the voltage of
the zener diode Z
1
.
T
A
= 25
o
C
FREE RUNNING FREQUENCY = 15734Hz
VOLTAGE AT TERM. 8 (THROUGH 1kΩ)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
0
10
20
30
40
50
60
70
POSITIVE PULSE WIDTH AT TERMINAL 1 (µs)
FIGURE 2. DUTY CYCLE AT THE PRE-DRIVE OUTPUT (TERMINAL
1) AS IT IS AFFECTED BY THE INPUT AT TERMINAL 8
V+
24V
620Ω
3kΩ
6800pF
+150V
4kΩ
10W
2.4kΩ
2
2.7kΩ
120kΩ
14kΩ
470µF
0.47µF
8.2kΩ
0.01µF
150kΩ
0.001µF
1.5kΩ
1
2
8
7
CA1394
3
470pF
270Ω
7.5kΩ
0.0027µF
SYNC
1.2kΩ
20V
P-P
5µs
60V
P-P
10µs
0.1µF
390kΩ
0.1µF
3.9kΩ
4
22Ω
6
5
FIGURE 3. TYPICAL CIRCUIT APPLICATION
8-12