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HMS2M32M16G-20 参数 Datasheet PDF下载

HMS2M32M16G-20图片预览
型号: HMS2M32M16G-20
PDF下载: 下载PDF文件 查看货源
内容描述: SRAM模块现象8字节( 2M ×32位) [SRAM MODULE 8Mbyte (2M x 32-Bit)]
分类和应用: 静态存储器
文件页数/大小: 10 页 / 283 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit  
HMS2M32M16G  
( /WE = V )  
TIMING WAVEFORM OF READ CYCLE  
IH  
tRC  
Address  
/CE  
tHZ(3,4,5)  
tAA  
tCO  
tLZ(4,5)  
tOHZ  
tOE  
/OE  
tOH  
tOLZ  
High-Z  
Data Out  
Data Valid  
tPD  
tPU  
50%  
lCC  
lSB  
Vcc Supply  
Current  
50%  
(Read Cycle)  
Notes  
1. /WE is high for read cycle.  
2. All read cycle timing is referenced from the last valid address to first transition address.  
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH  
or VOL levels.  
4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device  
to device.  
5. Transition is measured 200mV from steady state voltage with Load (B). This parameter is sampled and not 100%  
±
tested.  
6. Device is continuously selected with /CE = VIL.  
7. Address valid prior to coincident with /CE transition low.  
(/OE = Clock )  
TIMING WAVEFORM OF WRITE CYCLE  
tWC  
Address  
/OE  
tAW  
tWR(5)  
tCW(3)  
/CE  
tAS(4)  
tWP(2)  
/WE  
tDW  
tDH  
High-Z  
Data In  
Data Valid  
tOHZ  
tOW  
Data Out  
High-Z  
HANBit Electronics Co.,Ltd.