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HMN88D-120I 参数 Datasheet PDF下载

HMN88D-120I图片预览
型号: HMN88D-120I
PDF下载: 下载PDF文件 查看货源
内容描述: 非易失性SRAM模块为64Kbit ( 8K ×8位) , 28PIN DIP , 5V [Non-Volatile SRAM MODULE 64Kbit (8K x 8-Bit),28Pin DIP, 5V]
分类和应用: 静态存储器
文件页数/大小: 9 页 / 177 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit  
HMN88D  
FUNCTIONAL DESCRIPTION  
The HMN88D executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the  
address inputs(A0-A12) defines which of the 8,192 bytes of data is accessed. Valid data will be available to the eight data  
output drivers within tACC (access time) after the last address input signal is stable.  
When power is valid, the HMN88D operates as a standard CMOS SRAM. During power-down and power-up cycles, the  
HMN88D acts as a nonvolatile memory, automatically protecting and preserving the memory contents.  
The HMN88D is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs  
are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is  
terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle.  
/WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The /OE  
control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been  
enabled (/CE and /OE active) then /WE will disable the outputs in tODW from its falling edge.  
The HMN88D provides full functional capability for VCC greater than 4.5 V and write protects by 4.37 V nominal. Power-  
down/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold VPFD . When VCC  
falls below the VPFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become dont  
careand all outputs are high impedance. As VCC falls below approximately 3 V, the power switching circuit connects  
the lithium energy soure to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the  
power switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM  
operation can resume after VCC exceeds 4.5 volts.  
BLOCK DIAGRAM  
PIN DESCRIPTION  
A0-A12  
8K x 8  
/OE  
A0-A12 : Address Input  
/CE : Chip Enable  
SRAM  
Block  
DQ0-DQ7  
/WE  
VSS : Ground  
Power  
/CE  
DQ0-DQ7 : Data In / Data Out  
/WE : Write Enable  
/OE : Output Enable  
Power Fail  
VCC  
/CE  
Control  
Lithium  
Cell  
VCC: Power (+5V)  
NC : No Connection  
URL : www.hbe.co.kr  
Rev. 0.0 (April, 2002)  
2
HANBit Electronics Co.,Ltd