HANBit
HFDOM44P-xxxSx
Table 3.3 IDE Mode I/O Write Timing
Parameter
Data Setup before IOWR
Data Hold following IOWR
IOWR Width Time
Symbol
tsu(IOWR)
IEEE Symbol
tDVIWH
Min. ns
60
Max. ns
th(IOWR)
tlWHDX
tlWLIWH
tAVIWL
tlWHAX
tELIWL
tlWHEH
tAVISL
30
twI(OWR)
165
70
Address Setup before IOWR
Address Hold following IOWR
CE Setup before IOWR
tsuA(IOWR)
thA(IOWR)
20
tsuCE(IOWR)
thCE(IOWR)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
5
CE Hold following IOWR
20
IOIS16 Delay Falling from Address
35
35
IOIS16 Delay Rising from Address
tAVISH
NOTE: The maximum load on -IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum
time from -WAIT high to -IOWR high is 0nsec, but minimum -IOWR width must still be met.
A0-A10
-CE
-IOWR
-IOIS16
Din
Figure 3.2 IDE Mode I/O Write Timing Example
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REV 1.0 (August.2002)
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