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HFDOM40KB256 参数 Datasheet PDF下载

HFDOM40KB256图片预览
型号: HFDOM40KB256
PDF下载: 下载PDF文件 查看货源
内容描述: 40PIN闪存盘模块Min.8MB 〜 Max.1GB ,真正的IDE接口模式, 3.3V / 5.0V工作 [40Pin Flash Disk Module Min.8MB ~ Max.1GB, True IDE Interface Mode, 3.3V / 5.0V Operating]
分类和应用: 闪存
文件页数/大小: 30 页 / 138 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit  
HFDOM40KVxxx  
Implementation Note:  
Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller  
operating at the same addresses as the CompactFlash Storage Card. Following are some  
possible solutions to this problem for the PCMCIA implementation:  
1) Locate the CompactFlash Storage Card at a non-conflicting address, i.e. Secondary  
address (377) or in an independently decoded Address Space when a Floppy Disk Controller  
is located at the Primary addresses.  
2) Do not install a Floppy and a CompactFlash Storage Card in the system at the same time.  
3) Implement a socket adapter, which can be programmed to (conditionally) tri-state D7 of I/0  
address 3F7h/377h when a Compact Flash Storage Card is installed and conversely to tri-state  
D6-D0 of I/O address 3F7h/377h when a floppy controller is installed.  
4) Do not use the CompactFlash Storage Card’s Drive Address register. This may be  
accomplished by either a) If possible, program the host adapter to enable only I/O addresses  
1F0h-1F7h, 3F6h (or 170h-177h, 176h) to the CompactFlash Storage Card or b) if provided  
use an additional Primary / Secondary configuration in the CompactFlash Storage Card  
which does not respond to accesses to I/O locations 3F7h and 377h. With either of these  
implementations, the host software must not attempt to use information in the Drive Address  
Register.  
Bit 6 (-WTG): this bit is 0 when a write operation is in progress, otherwise, it is 1.  
Bit 5 (-HS3): this bit is the negation of bit 3 in the Drive/Head register.  
Bit 4 (-HS2): this bit is the negation of bit 2 in the Drive/Head register.  
Bit 3 (-HS1): this bit is the negation of bit 1 in the Drive/Head register.  
Bit 2 (-HS0): this bit is the negation of bit 0 in the Drive/Head register.  
Bit 1 (-nDS1): this bit is 0 when drive 1 is active and selected.  
Bit 0 (-nDS0): this bit is 0 when the drive 0 is active and selected.  
4. ATA COMMAND  
CF-ATA Command Set  
Table summarizes the CF-ATA command set with the paragraphs that follow describing the  
individual commands and the task file for each.  
Table:CF-ATA Command Set  
Class  
COMMAND  
Code  
FR  
-
SC  
-
SN  
-
CY  
-
DH  
D
D
Y
LBA  
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Check Power Mode  
E5h or 98h  
-
-
Execute Drive Diagnostic 90h  
-
-
-
-
Format Track  
Identify Drive  
Idle  
50h  
-
Y
-
-
Y
-
Y
-
ECh  
-
-
D
D
D
Y
E3h or 97h  
E1h or 95h  
-
Y
-
-
-
-
Idel Immediate  
-
-
-
-
Initialize Drive Parameters 91h  
-
Y
-
-
-
-
Read Buffer  
E4h  
-
-
-
D
Y
-
Read Long Sector  
Read Multiple  
Read Sector(s)  
Read Verify Sector(s)  
Recalibrate  
22h or 23h  
C4h  
-
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
Y
Y
Y
Y
-
-
Y
Y
Y
-
Y
20h or 21h  
40h or 41h  
1Xh  
-
Y
-
Y
-
D
D
Y
Request Sence  
Seek  
03h  
-
-
-
-
-
7Xh  
-
-
Y
-
Y
-
Y
-
Set Features  
EFh  
Y
-
-
D
D
Set Multiple Mode  
C6h  
Y
-
-
-
URL:www.hbe.co.kr  
13 / 13  
HANBit Electronics Co., Ltd.  
Rev. 1.1 (December, 2003)