NMOS linear image sensor
s
Driver circuit
S3901/S3904 series do not require any DC voltage supply
for operation. However, the Vss, Vsub and all NC terminals
must be grounded. A start pulse
φst
and 2-phase clock pulses
φ1, φ2
are needed to drive the shift register. These start and
clock pulses are positive going pulses and CMOS logic com-
patible.
The 2-phase clock pulses
φ1, φ2
can be either completely
separated or complementary. However, both pulses must not
be “High” at the same time.
A clock pulse space (X1 and X2 in “sTiming chart for driver
circuit”) of a “rise time/fall time - 20” ns or more should be
input if the rise and fall times of
φ1, φ2
are longer than 20 ns.
The
φ1
and
φ2
clock pulses must be held at “High” at least
200 ns. Since the photodiode signal is obtained at the rise of
each
φ2
pulse, the clock pulse frequency will equal the video
data rate.
S3901/S3904 series
The amplitude of start pulse
φst
is the same as the
φ1
and
φ2
pulses. The shift register starts the scanning at the “High”
level of
φst,
so the start pulse interval determines the length of
signal accumulation time. The
φst
pulse must be held “High”
at least 200 ns and overlap with
φ2
at least for 200 ns. To
operate the shift register correctly,
φ2
must change from the
“High” level to the “Low” level only once during “High” level of
φst.
The timing chart for each pulse is shown in “sTiming
chart for driver circuit”.
s
End of scan
The end of scan (EOS) signal appears in synchronization
with the
φ2
timing right after the last photodiode is addressed,
and the EOS terminal should be pulled up at 5 V using a 10
kΩ resistor.
s
Timing chart for driver circuit
st
1
2
V s (H)
V s (L)
V
V
V
V
1 (H)
1 (L)
2 (H)
2 (L)
tpw s
tpw 1
tpw 2
tvd
Active video output
s
Video bias voltage margin
10
8
Video bias voltage (V)
6
End of scan
c
Re
4
m
om
en
d
de
bia
s
x
Ma
.
tr s
st
tf s
Video bias range
2
tr 1
tf 1
1
X1
2
t ov
tr 2
X2
tf 2
MIN.
0
4
5
6
7
8
9
10
Clock pulse amplitude (V)
s
Signal readout circuit
There are two methods for reading out the signal from an NMOS
linear image sensor. One is a current detection method using
the load resistance and the other is a current integration method
using a charge amplifier. In either readout method, a positive
bias must be applied to the video line because photodiode
anodes of NMOS linear image sensors are set at 0 V (Vss).
“sVideo bias voltage margin” shows a typical video bias volt-
age margin. As the clock pulse amplitude is higher, the video
bias voltage can be set larger so the saturation charge can be
increased. The rise and fall times of the video output waveform
can be shortened if the video bias voltage is reduced while the
clock pulse amplitude is still higher. When the amplitude of
φ1,
φ2
and
φst
is 5 V, setting the video bias voltage at 2 V is recom-
mended.
To obtain good linearity, using the current integration method is
advised. In this method, the integration capacitance is reset to
the reference voltage level immediately before each photodiode
is addressed and the signal charge is then stored as an integra-
tion capacitive charge when the address switch turns on.
“sReadout circuit example” and “sTiming chart” show a typi-
cal current integration circuit and its pulse timing chart. To en-
KMPDC0022EA
KMPDB0043EA
sure stable output, the rise of a reset pulse must be delayed at
least 50 ns from the fall of
φ2.
Hamamatsu provides the following driver circuits and related
products (sold separately).
Product
Type No.
Content
Feature
name
High-speed
H igh-speed operation
C7883
driver circuit Single pow er supply
(+15 V ) operation
C7883
C7883G
+ C8225-01 C om pact
Precision
C7884
Low noise
driver circuit
Driver
G ood output linearity
circuit
C7884
Boxcar w aveform output
C7884G
+ C8225-01
H igh precision
C7884-01
U ltra-low noise
driver circuit
G ood output linearity
C7884-01
Boxcar w aveform output
C 7 88 4G -01
+ C8225-01
Pulse
C 7883,
C8225-01
generator
C 7884 series
C 7883 to
Cable
A8226
BNC, length 1 m
C 7885 series
5
HAMAMATSU [ HAMAMATSU CORPORATION ]
