ISSUED DATE :2005/08/10
REVISED DATE :2006/05/15C
Application Circuit
FLIP-FLOP
GSCNE555
Application Notes
The application circuit shows astable mode configuration.
Pin 6 (Threshold) is tied to Pin 2 (Trigger) and Pin 4 (Reset) is tied to V
CC
(Pin 8). The external capacitor C1
of Pin 6 and Pin 2 charges through RA, RB and discharge through RB only. In the internal circuit of
GSCNE555, one input of the upper comparator is at voltage of 2/3V
CC
(R1=R2=R3), another input is
connected to Pin 6. As soon as C1 is charging to higher than 2/3V
CC
, transistor Q1 is turned ON and
discharge C1 to collector voltage of transistor Q1. Therefore, the flip-flop circuit is reset and output is low. One
input of lower comparator is at voltage of 1/3V
CC
, discharge transistor Q1 turn off and C1 charges through RA
and RB. Therefore, flip-flop circuit is set output high.
That is, when C1 charges through RA and RB, output is high and when C1 discharge through RB, output is
low. The charge time (output is high) t1 is 0.693 (RA+RB) C1 and the discharge time (output is low) T2 is
0.693RB*C1.
Vcc-
1
Vcc
3
In
Vcc- 2 Vcc
1
3
=0.693
T1=0.693*(RA+RB)*C1
T2=0.693*RB*C1
Thus the total period time T is given by
T=T1+T2=0.693(RA+2RB)*C1
Then the frequency of astable mode is given by
f=
1
T
=
1.44
(RA+2RB)*C1
The duty cycle is given by
D.C. =
T2
T
=
RB
RA+2RB
Important Notice:
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of GTM.
GTM reserves the right to make changes to its products without notice.
GTM semiconductor products are not warranted to be suitable for use in life-support Applications, or systems.
GTM assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.
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GSCNE555
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