ISSUED DATE :2006/06/14
REVISED DATE :
ERASE (ERASE):
The Erase (ERASE) instruction clears the designated memory location to a logic ‘1’ state.
After the Op Code and address location is inputted, the chip will enter into an erase cycle. When the cycle
completes, the chip will automatically enter into standby mode.
WRITE (WRITE):
The Write (WRITE) instruction is used to write to a specific memory location. If word mode
(x16) is selected, then 16 bits of data will be written into the location. If byte mode (x8) is chosen, then 8 bits of
data will be written into the location. The write cycle will begin automatically after the 8 or 16 bits are shifted
into the chip.
ERASE ALL (ERAL):
The Erase All (ERAL) instruction is primarily used for testing purposes and only
functions when V
CC
=4.5V to 5.5V. This instruction will clear the entire memory array to ‘1’.
WRITE ALL (WRAL):
The Write All (WRAL) instruction will program the entire memory array according to the 8
or 16-bit data pattern provided. The instruction will only be valid when V
CC
=4.5V to 5.5V.
ERASE/WRITE DISABLE (EWDS):
The Erase/Write Disable (EWDS) instruction blocks any kind of erase or
program operations from modifying the contents of the memory array. This instruction should be executed after
erasing or programming to prevent accidental data loss.
Note also that the READ instruction will operate regardless of whether the chip is disabled from program and
write operations.
To determine whether the chip has completed an erase or write operation, the CS signal can be pulled LOW
for a minimum of 250ns (t
CS
) and then pulled back HIGH to enter Ready/Busy mode. If the chip is currently in
the programming cycle, t
WP
, then the DO pin will go low (logical “0”). When the write cycle completes, the DO
pin is pulled high (logical “1”) to indicate that the part can receive anther instruction. Note that the Ready/Busy
polling cannot be done if the chip has already finished and returned back to standby mode.
Ready/Busy
Timing Diagrams
Synchronous Data Timing
Note (1): This is the minimum SK period.
Organization Key for TIMING Diagrams
I/O
A
N
D
N
GSC93BC46(1K)
X8
X16
A
6
A
5
D
7
D
15
GSC93BC56(2K)
X8
X16
(1)
A
8
A
7
(2)
D
7
D
15
GSC93BC66(4K)
X8
X16
A
8
A
7
D
7
D
15
Note:
1. A
8
is a DON’T CARE value, but the extra clock is required.
2. A
7
is a DON’T CARE value, but the extra clock is required.
GSC93BC46/56/66
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