GS882ZV18/36BB/D-333/300/250/200
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
V
– 0.2 V
Input high level
Input low level
DQ
DD
0.2 V
1 V/ns
*
50Ω
Input slew rate
30pF
V
V
/2
Input reference level
DDQ
V
/2
DDQ
/2
Output reference level
DDQ
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
V
0.6 * V
V
+0.3
DD
Test Port Input High Voltage
V
V
1
1
IHJ
DD
V
0.3 * V
1
Test Port Input Low Voltage
–0.3
–300
–1
ILJ
DD
I
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
1.7
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
—
0.4
—
V
OLJ
V
V
– 100 mV
DDQ
V
OHJC
V
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V
+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
3. 0 V ≤ V ≤ V
IN
ILJn
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OHJC
Rev: 1.03 3/2005
26/33
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
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