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GS864018/32/36T-300/250/200/167
Mode Pin Functions
Mode Name
Pin Name
State
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
L
Burst Order Control
LBO
H
L
H or NC
L or NC
H
Output Register Control
FT
ZZ
Active
Power Down Control
Standby, I = I
DD SB
L
Dual Cycle Deselect
Single Cycle Deselect
Single/Dual Cycle Deselect Control
FLXDrive Output Impedance Control
9th Bit Enable
SCD
ZQ
H or NC
L
High Drive (Low Impedance)
H or NC
L or NC
H
Low Drive (High Impedance)
Activate DQPx I/Os (x18/x3672 mode)
Deactivate DQPx I/Os (x16/x3272 mode)
PE
Note:
There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00 9/2004
7/24
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
