GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
TDI
tTH
tTH
tTS
tTS
TMS
TDO
tTKQ
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
TCK Cycle Time
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
50
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
tTH
—
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
Rev: 2.21 11/2004
30/38
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
