Preliminary
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
GS8161Z18/32/36BD 165-Bump BGA Pin Description
Symbol
A0, A1
A
Type
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
I
I
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA, BB, BC, BD
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
NC
CK
Clock Input Signal; active high
Clock Input Buffer Enable; active low
Write Enable; active low
CKE
W
I
I
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
Burst address counter advance enable; active high
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Scan Test Mode Select
ADV
ZZ
I
I
FT
I
LBO
TMS
TDI
TDO
TCK
MCH
I
I
I
Scan Test Data In
O
I
Scan Test Data Out
Scan Test Clock
—
I
Must Connect High
V
Core power supply
DD
V
I
I
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 1.00 9/2004
9/37
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
