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GS816036BGT-250IV 参数 Datasheet PDF下载

GS816036BGT-250IV图片预览
型号: GS816036BGT-250IV
PDF下载: 下载PDF文件 查看货源
内容描述: 1M ×18 , 512K ×32 , 512K ×36 18MB同步突发静态存储器 [1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 23 页 / 984 K
品牌: GSI [ GSI TECHNOLOGY ]
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Preliminary  
GS8160xxBT-xxxV  
Sleep Mode  
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,  
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to  
low, the SRAM operates normally after ZZ recovery time.  
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of  
SB  
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become  
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.  
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending  
SB  
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated  
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands  
may be applied while the SRAM is recovering from Sleep mode.  
Sleep Mode Timing  
tKH  
tKC  
tKL  
CK  
Setup  
Hold  
ADSP  
ADSC  
tZZR  
tZZS  
tZZH  
ZZ  
Application Tips  
Single and Dual Cycle Deselect  
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with  
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually  
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste  
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at  
bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.  
Rev: 1.01 5/2006  
19/23  
© 2004, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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