GS72116ATP/J/T/U
TSOP-II 128K x 16-Pin Configuration
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A4
A3
A5
2
A6
3
A2
A7
4
A1
OE
Top view
5
A0
UB
6
CE
LB
7
DQ1
DQ2
DQ3
DQ4
VDD
DQ16
DQ15
DQ14
8
9
10
11
12
13
14
15
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
44-pin
VSS
TSOP II
DQ5
DQ6
DQ7
DQ8
WE
16
17
18
A15
A14
A13
A12
A16
A8
19
20
21
22
A9
A10
A11
NC
Package TP
Block Diagram
A0
Row
Decoder
Memory Array
Address
Input
Buffer
Column
Decoder
A16
CE
WE
OE
UB
LB
I/O Buffer
Control
_____
_____
DQ16
DQ1
Rev: 1.04a 10/2002
3/18
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
