GS71116AGP-12IT 参数 Datasheet PDF下载

GS71116AGP/U

Block Diagram

A

0

Address

Input

Buffer

Row

Decoder

Memory Array

A

15

CE

WE

Control

OE

UB

_____

Column

Decoder

I/O Buffer

DQ

1

DQ

16

Truth Table

CE

H

OE

X

WE

X

LB

X

L

UB

X

L

H

L

L

H

L

X

H

DQ

1

to DQ

8

Not Selected

Read

Read

High Z

Write

Write

Not Write, High Z

High Z

High Z

DQ

9

to DQ

16

Not Selected

Read

High Z

Read

Write

Not Write, High Z

Write

High Z

High Z

V

DD

Current

ISB

1

, ISB

2

L

L

H

L

H

L

L

X

L

L

H

I

DD

L

L

Note:

X: “H” or “L”

H

X

H

X

X

H

Rev: 1.10 1/2013

2/13

© 2001, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.