GS71108AU
Block Diagram
A
0
Address
Input
Buffer
Row
Decoder
Memory Array
A
16
CE
WE
OE
Column
Decoder
Control
I/O Buffer
DQ
1
DQ
8
Truth Table
CE
H
L
L
L
Note:
X: “H” or “L”
OE
X
L
X
H
WE
X
H
L
H
DQ
1
to DQ
8
Not Selected
Read
Write
High Z
V
DD
Current
ISB
1
, ISB
2
I
DD
Rev: 1.10a 3/2011
2/11
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.