GS71108ATP/U
AC Test Conditions
Parameter
Input high level
Input low level
Input rise time
Input fall time
Input reference level
Output reference level
Output load
Conditions
V
IH
= 2.4 V
V
IL
= 0.4 V
tr = 1 V/ns
tf = 1 V/ns
1.4 V
1.4 V
Fig. 1& 2
Output Load 1
DQ
50
VT = 1.4 V
30pF
1
Output Load 2
3.3 V
DQ
5pF
1
589
434
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in
Fig. 1
unless otherwise noted.
3. Output load 2 for t
LZ
, t
HZ
, t
OLZ
and t
OHZ
AC Characteristics
Read Cycle
Parameter
Read cycle time
Address access time
Chip enable access time (CE)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
Symbol
t
RC
t
AA
t
AC
t
OE
t
OH
t
LZ
*
t
OLZ
*
t
HZ
*
t
OHZ
*
-7
Min
7
—
—
—
3
3
0
—
—
Max
—
7
7
3
—
—
—
3.5
3
Min
8
—
—
—
3
3
0
—
—
-8
Max
—
8
8
3.5
—
—
—
4
3.5
Min
10
—
—
—
3
3
0
—
—
-10
Max
—
10
10
4
—
—
—
5
4
Min
12
—
—
—
3
3
0
—
—
-12
Max
—
12
12
5
—
—
—
6
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
* These parameters are sampled and are not 100% tested
Rev: 1.10 3/2009
5/13
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
