GS71024T/U
Write Cycle 1: WE control
t
WC
Address
t
AW
OE
t
CW
CE1
(*1)
V/S
t
AS
WE
Data In
t
WHZ
Data Out
High impedance
t
WR
t
VS
t
VW
t
WP
(*2)
t
DW
Data valid
t
DH
t
WLZ
(*3)
(*3)
*1 CE1 represents both CE1 low and CE2 high.
*2 Write is executed when both CE1 and WE are at low simultaneously.
*3 Do not apply the data input voltage to the output while DQ pin is in output condition.
Write Cycle 2: CE control
t
WC
Address
t
AW
OE
t
AS
CE1
(*1)
t
VW
V/S
WE
Data In
Data Out
t
WP
t
DW
Data valid
t
WR1
t
CW
t
DH
High impedance
*1 CE1 represents both CE1 low and CE2 high.
Rev: 1.05 11/2004
9/13
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
