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GS4576S18GL-18I 参数 Datasheet PDF下载

GS4576S18GL-18I图片预览
型号: GS4576S18GL-18I
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX18, CMOS, PBGA144, ROHS COMPLIANT, UBGA-144]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 63 页 / 2207 K
品牌: GSI [ GSI TECHNOLOGY ]
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GS4576S09/18L
Power–Up Initialization Flow Chart
Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
V
DD
and V
EXT
ramp
V
DDQ
ramp
Apply V
REF
and V
TT
Apply stable CK/CK and DK/DK
Wait at least 200s
Issue MRS command—A10–A17 must be Low
Issue MRS command—A10–A17 must be Low
Desired load mode register with A10–A17 Low
Assert NOP for tMRSC
Issue AUTO REFRESH to bank 0
Issue AUTO REFRESH to bank 1
Issue AUTO REFRESH to bank 2
Issue AUTO REFRESH to bank 3
Issue AUTO REFRESH to bank 4
Issue AUTO REFRESH to bank 5
Issue AUTO REFRESH to bank 6
Issue AUTO REFRESH to bank 7
Wait 1024 NOP commands
*
Valid command
MRS commands
must be on
consecutive
clock cycles
Voltage rails can
be applied
simultaneously
*Note:
The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP commands) does not matter. As is required for any
operation, tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank.
Rev: 1.03 11/2013
8/63
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.