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GS4576C18L-25T 参数 Datasheet PDF下载

GS4576C18L-25T图片预览
型号: GS4576C18L-25T
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX18, CMOS, PBGA144, UBGA-144]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 2381 K
品牌: GSI [ GSI TECHNOLOGY ]
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GS4576C09/18/36L
Ball Descriptions (Continued)
Symbol
QVLD
TDO
V
DD
V
DDQ
V
EXT
V
SS
V
TT
A22
DNU
NF
Type
Output
Output
Supply
Supply
Supply
Supply
Description
Data Valid—The
QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx.
IEEE 1149.1 Test Output—JTAG
output. This ball may be left as no connect if the JTAG function is not
used.
Power Supply—Nominally,
1.8 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
DQ Power Supply—Nominally,
1.5 V or 1.8 V. Isolated on the device for improved noise immunity. See
the DC Electrical Characteristics and Operating Conditions section for range.
Power Supply—Nominally,
2.5 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
Ground
Power Supply—Isolated
termination supply. Nominally, V
DDQ
/2. See the DC Electrical Characteristics
and Operating Conditions section for range.
Reserved for Future Use—This
signal is not connected and may be connected to ground.
Do Not Use—These
balls may be connected to ground.
No Function—These
balls can be connected to ground.
Rev: 1.04 11/2013
6/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.