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GS4288S18GL-25I 参数 Datasheet PDF下载

GS4288S18GL-25I图片预览
型号: GS4288S18GL-25I
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 16MX18, CMOS, PBGA144, ROHS COMPLIANT, UBGA-144]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 63 页 / 2189 K
品牌: GSI [ GSI TECHNOLOGY ]
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Preliminary
GS4288S09/18L
Operations
Initialization
A specific power-up and initialization sequence must be observed. Other sequences may result in undefined operations or
permanent damage to the device.
Power-up:
1. Apply power (V
EXT
, V
DD
, V
DDQ
, V
REF
, V
TT
) . Start clock after the supply voltages are stable. Apply V
DD
and V
EXT
before or
at the same time as V
DDQ
1
. Apply V
DDQ
before or at the same time as V
REF
and V
TT
. The chip starts internal initlization
only after both voltages approach their nominal levels. CK/CK must meet V
ID
(
DC
)
prior to being applied
2
. Apply only
NOP commands to start. Ensuring CK/CK meet V
ID
(
DC
)
while loading NOP commands guarantees that the LLDRAM II
will not receive damaging commands during initialization.
2. Idle with continuing NOP commands for 200s (MIN).
3. Issue three or more consecutive MRS commands: two or more dummies plus one valid MRS. The consecutive MRS
commands will reset internal logic of the LLDRAM II.
t
MRSC does not need to be met between these consecutive
commands. Address pins should be held Low during the dummy MRS commands.
4.
t
MRSC after the valid MRS, issues an AUTO REFRESH command to all 8 banks in any order (along with 1024 NOP
commands) prior to normal operation. As always,
t
RC must be met between any AUTO REFRESH and any subsequent
valid command to the same bank.
Notes:
1. It is possible to apply V
DDQ
before V
DD
. However, when doing this, the Ds, DM, Qs and all other pins with an output driver,
will go High instead of tri-stating. These pins will remain High until V
DD
is at the same level as V
DDQ
. Care should be taken to
avoid bus conflicts during this period.
2.
If V
ID
(
DC
)
on CK/CK can not be met prior to being applied to the LLDRAM II, placing a large external resistor from CS to V
DD
is a viable option for ensuring the command bus does not receive unwanted commands during this unspecified state.
Rev: 1.02 3/2013
6/63
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.