Preliminary
GS4288C09/18/36L
Ball Descriptions (Continued)
Symbol
QVLD
TDO
V
DD
V
DDQ
V
EXT
V
SS
V
TT
A21, A22
DNU
NF
Type
Output
Output
Supply
Supply
Supply
Supply
—
—
—
—
Description
Data Valid—The
QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx.
IEEE 1149.1 Test Output—JTAG
output. This ball may be left as no connect if the JTAG function is not
used.
Power Supply—Nominally,
1.8 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
DQ Power Supply—Nominally,
1.5 V or 1.8 V. Isolated on the device for improved noise immunity. See
the DC Electrical Characteristics and Operating Conditions section for range.
Power Supply—Nominally,
2.5 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
Ground
Power Supply—Isolated
termination supply. Nominally, V
DDQ
/2. See the DC Electrical Characteristics
and Operating Conditions section for range.
Reserved for Future Use—This
signal is not connected and may be connected to ground.
Do Not Use—These
balls may be connected to ground.
No Function—These
balls can be connected to ground.
Operations
Initialization
A specific power-up and initialization sequence must be observed. Other sequences may result in undefined operations or
permanent damage to the device.
Power-up:
1. Apply power (V
EXT
, V
DD
, V
DDQ
, V
REF
, V
TT
) . Start clock after the supply voltages are stable. Apply V
DD
and V
EXT
before or
at the same time as V
DDQ
1
. Apply V
DDQ
before or at the same time as V
REF
and V
TT
. The chip starts internal initlization
only after both voltages approach their nominal levels. CK/CK must meet V
ID
(
DC
)
prior to being applied
2
. Apply only
NOP commands to start. Ensuring CK/CK meet V
ID
(
DC
)
while loading NOP commands guarantees that the LLDRAM II
will not receive damaging commands during initialization.
2. Idle with continuing NOP commands for 200s (MIN).
3. Issue three or more consecutive MRS commands: two or more dummies plus one valid MRS. The consecutive MRS
commands will reset internal logic of the LLDRAM II.
t
MRSC does not need to be met between these consecutive
commands. Address pins should be held Low during the dummy MRS commands.
Rev: 1.02 3/2013
6/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GSI [ GSI TECHNOLOGY ]
