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GS4288C36L-25T 参数 Datasheet PDF下载

GS4288C36L-25T图片预览
型号: GS4288C36L-25T
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 8MX36, CMOS, PBGA144, UBGA-144]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 2384 K
品牌: GSI [ GSI TECHNOLOGY ]
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Preliminary  
GS4288C09/18/36L  
Commands  
Valid control commands are listed below. Any input commands not shown are illegal or reserved. All inputs must meet specified  
setup and hold times around the true crossing of CK.  
Description of Commands  
Command  
Description  
Notes  
The NOP command is used to perform a no operation to the LLDRAM II, which essentially deselects the  
chip. Use the NOP command to prevent unwanted commands from being registered during idle or wait  
states. Operations already in progress are not affected. Output values depend on command history.  
DSEL/NOP  
1
The Mode Register is set via the address inputs A0–A17. See the Mode Register Definition diagrams for  
further information. The MRS command can only be issued when all banks are idle and no bursts are in  
progress.  
MRS  
2
The Read command is used to initiate a burst read access to a bank. The value on the BA0–BA2 inputs  
selects the bank, and the address provided on inputs A0–An selects the data location within the bank.  
READ  
The Write command is used to initiate a burst write access to a bank. The value on the BA0–BA2 inputs  
selects the bank, and the address provided on inputs A0–An selects the data location within the bank.  
Input data appearing on the DQ is written to the memory array subject to the DM input logic level  
appearing coincident with the data. If the DM signal is registered Low, the corresponding data will be  
written to memory. If the DM signal is registered High, the corresponding data inputs will be ignored (that  
is, this part of the data word will not be written).  
WRITE  
AREF  
2
The AREF command is used during normal operation of the LLDRAM II to refresh the memory content  
of a bank. The command is non-persistent, so it must be issued each time a refresh is required. The  
value on the BA0–BA2 inputs selects the bank. The refresh address is generated by an internal refresh  
controller, effectively making each address bit a “Don’t Care” during the AREF command.  
See the Auto Refresh section for more details.  
Notes:  
1. When the chip is deselected, internal NOP commands are generated and no commands are accepted.  
2. For the value of “n”, see Address Widths at Different Burst Lengths table.  
Command Table  
Operation  
Command  
CS  
WE  
REF  
BA0–BA2  
A0–An  
Device Deselect/No Operation  
DSEL/NOP  
MRS  
H
L
L
L
L
X
L
X
L
X
X
1
MRS  
Read  
CODE  
X
1, 3  
1, 2  
1, 2  
1
READ  
H
L
H
H
L
A
A
X
BA  
BA  
BA  
Write  
WRITE  
AREF  
Auto Refresh  
H
Notes:  
1. X= Don’t Care; H = Logic High; L = Logic Low; A = Valid Address; BA = Valid Bank Address.  
2. For the value of “n”, see Address Widths at Different Burst Lengths table.  
3. Only A0–A17 are used for the MRS command.  
Rev: 1.02 3/2013  
14/62  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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