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GS4288C36GL-18I 参数 Datasheet PDF下载

GS4288C36GL-18I图片预览
型号: GS4288C36GL-18I
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 8MX36, CMOS, PBGA144, ROHS COMPLIANT, UBGA-144]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 2384 K
品牌: GSI [ GSI TECHNOLOGY ]
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Preliminary
GS4288C09/18/36L
Power–Up Initialization Sequence
VEXT
VDD
VDDQ
VREF
VTT
200us Min
tCK
tCKH
CK
CK
tDKL
tDK
DK
DK
Command
ADDR
BA
DM
DQ
NOP
NOP
MRS
CODE(1,2)
tDKH
tCKL
Mode Initialization
tMRSC
Refresh
1024 Cycles NOP Cycles Min
All Banks(5)
MRS
CODE(1,2)
MRS
CODE(2)
NOP
AREF
AREF
NOP
AC
ADDR
Bank 0
Bank 7
Valid
Notes:
1.
2.
3.
4.
5.
Recommend all address pins held Low during dummy MRS commands.
A10–A17 must be Low.
DLL must be reset if tCK or V
DD
are changed.
CK and CK must be separated at all times to prevent bogus commands from being issued.
The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP commands) does not matter. As is required for any operation,
tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank.
Rev: 1.02 3/2013
8/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.