Global Mixed-mode Technology Inc.
Pin Description
G916
PIN
G916-XXX
NAME
FUNCTION
G916
1
1
IN
Regulator Input. Supply voltage can range from +2.5V to +6.0V. Bypass with 1µF to GND
Ground. This pin also functions as a heatsink. Solder to large pads or the circuit board
ground plane to maximize thermal dissipation.
2
3
2
GND
Active-Low Shutdown Input. A logic low reduces the supply current to less than 1µA. Connect to IN
for normal operation.
SHDN
3
Feedback Input for Setting the Output Voltage. Connect to GND to set the output voltage to
4
SET the preset output voltage. Connect to an external resistor divider for adjustable-output op-
eration.
This is a reference bypass pin. It should connect external 10nF capacitor to GND to reduce
4
5
BYP
output noise. Bypass capacitor must be no less than 1nF. (CBYP≥ 1nF)
Regulator Output. Sources up to 300mA. Bypass with a 1µF, ＜0.2Ω typical ESR capacitor
5
OUT
to GND.
feedback voltage force to be the same as the 1.25V
bandgap reference. The output voltage, VOUT, is then
given by the following equation:
Detailed Description
The block diagram of the G916 is shown in Figure 1. It
consists of an error amplifier, 1.25V bandgap reference,
PMOS output transistor, internal feedback voltage divider,
mode comparator, shutdown logic, over current protec-
tion circuit, and over temperature protection circuit.
VOUT = 1.25 (1 + R1/R2).
(1)
Alternatively, the relationship between R1 and R2 is
given by:
The mode comparator compares the SET pin voltage
with an internal 350mV reference. If the SET pin volt-
age is less than 350mV, the internal feedback voltage
divider’s central tap is connected to the non-inverting
input of the error amplifier. The error amplifier com-
pares non-inverting input with the 1.25V bandgap ref-
erence. If the feedback voltage is higher than 1.25V,
the error amplifier’s output becomes higher so that the
PMOS output transistor has a smaller gate-to-source
voltage (VGS). This reduces the current carrying capa-
bility of the PMOS output transistor, as a result the
output voltage decreases until the feedback voltage is
equal to 1.25V. Similarly, when the feedback voltage is
less than 1.25V, the error amplifier causes the output
PMOS to source more current to pull the feedback
voltage up to 1.25V. Thus, through this feedback ac-
tion, the error amplifier, output PMOS, and the voltage
dividers effectively form a unity-gain amplifier with the
R1 = R2 (VOUT /1.25 - 1).
(2)
For the reasons of reducing power dissipation and
loop stability, R2 is chosen to be 100KΩ. For G916,
R1 is 164K, and the pre-set VOUT is 3.30V.
When external voltage divider is used, as shown in
Figure 2, the SET pin voltage will be larger than
350mV. The non-inverting input of the amplifier will be
connected to the external voltage divider. However,
the operation of the feedback loop is the same, so that
the conditions of Equations 1 and 2 are still true. The
output voltage is still given by Equation 1.
For G916-XXX, adjust the internal reference and in-
ternal voltage divider. It provides a fixed mode output
ranging from 1.2V to 5V.
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.7
Jan 25, 2006
8
GMT [ GLOBAL MIXED-MODE TECHNOLOGY INC ]
