Global Mixed-mode Technology Inc.
G696/G697
Pin Description
PIN
NAME
FUNCTION
RESET Output remains low while VCC is below the reset threshold, and for delay time set by CD
after VCC rises above the reset threshold.
RESET (G696L/G697L)
1
RESET Output remains high while VCC is below the reset threshold, and for delay time set by CD
after VCC rises above the reset threshold.
RESET (G696H)
2
3
4
5
VCC
GND
NC
Supply Voltage (+5V, +3.3V, +3.0V)
Ground
No Connection.
CD
External Programmable time delay is set by the capacitor connect to CD pin.
Detailed Description
A microprocessor’s (µP’s) reset input starts the µP in a
known state. The G697L/G696L/G696H assert reset to
prevent code-execution errors during power-up,
power-down, or brownout conditions. They assert a
reset signal whenever the VCC supply voltage declines
below a preset threshold (VTH-), keeping it asserted for
time delay set by capacitor connected to CD pin, after
VCC has risen above the high reset threshold VTH+
(VTH-+VHYS). The G697L uses an open-drain output,
and the G696L/G696H have a push-pull output stage.
must be valid down to 0V, adding a pull-down resistor
to RESET causes any stray leakage currents to flow
to ground, holding RESET low (Figure 4). R1’s value
is not critical; 100kΩ is large enough not to load
RESET and small enough to pull RESET to ground.
A 100kΩ pull-up resistor to VCC is also recommended
for the G697L if RESET is required to remain valid
for VCC < 0.8V.
Connect a pull-up resistor on the G697L’s RESET out-
put to any supply between 0 and 5.5V.
VCC
The time delay is set by external capacitor CD, and
internal pull up current ICD. When the voltage at CD
pin exceeds the buffer threshold, typically 1.25V, the
VCC
VCC
RPULL-UP
µP
G697
RESET output high (RESET output low). The volt-
age detector and buffer have built-in hysterisis to
prevent erratic reset operation. The formula of time
delay is T (ms) ≅ 1685 CD (µF). Fig1 and Fig2 show a
timing deagram and a Functional Block.
RESET MOTOROLA
RESET
INPUT
68HCXX
GND
GND
VCC
Figure 4. Interfacing to µPs with Bidirectional Re-
G696
set I/O
RESET
+5.0V
R1
100k
+3.3V
GND
VCC
VCC
RPULL-UP
5V SYSTEM
G697
Figure3. RESET Valid to VCC = Ground Circuit
Ensuring a Valid Reset Output Down to VCC = 0
RESET
INPUT
RESET
When VCC falls below 0.8V, the G696 RESET output
no longer sinks current-it becomes an open circuit.
Therefore, high-impedance CMOS logic inputs con-
GND
GND
nected to RESET can drift to undetermined voltages.
This presents no problem in most applications since
most µP and other circuitry is inoperative with VCC
Figure 5. G697L Open-Drain RESET Output Allows
Use with Multiple Supplies
below 0.8V. However, in applications where RESET
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.8
May 10, 2006
8
GMT [ GLOBAL MIXED-MODE TECHNOLOGY INC ]
