Global Mixed-mode Technology Inc.
G570
Parameter Measurement Information
VPP
VCC
CL
CL
LOAD CIRCUIT
LOAD CIRCUIT
VDD
VDD
50%
50%
LATCH
GND
LATCH
GND
toff
toff
ton
ton
VI(12V)
GND
VI(5V)
VO(xVPP)
VO(xVCC)
90%
90%
10%
10%
GND
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Figure 1. Test Circuits and Voltage Waveforms
Table of Timing Diagrams
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA
LATCH
CLOCK
Note:Data is clocked in on the positive leading edge of the clock. The latch should occur before the next
positive leading edge of the clock. For definition of D0 to D8, see the control logic table.
Figure 2. Serial-Interface Timing
Ver 1.0
Nov 09, 2000
TEL: 886-3-5788833
http://www.gmt.com.tw
5
GMT [ GLOBAL MIXED-MODE TECHNOLOGY INC ]
