Global Mixed-mode Technology Inc.
G2995
Pin Description
NUMBER
NAME
NC
FUNCTION
1
2
3
4
5
6
7
8
GND
Ground
VSENSE
VREF
VDDQ
AVIN
Feedback pin for regulating VTT
Buffered output that is a reference output of VDDQ/2
Input for internal reference which equals to VDDQ/2
Analog input pin
PVIN
Power input pin
VTT
Output voltage for connection to termination resistors, equal to VDDQ/2
Block Diagram
VDDQ
AVIN
PVIN
50k
+
+
VTT
VREF
-
-
50k
VSENSE
GND
Description
VTT
VDD
The G2995 is a linear bus termination regulator de-
signed to meet the JEDEC SSTL-2 and SSTL-3 (Se-
ries Stub Termination Logic) specifications for termina-
tion of DDR-SDRAM. The output, VTT, is capable of
sinking and sourcing current while regulating the out-
put voltage equal to VDDQ/2. The G2995 is designed
to maintain the excellent load regulation and with fast
response time to minimum the transition preventing
shoot-through. The G2995 also incorporates two dis-
tinct power rails that separates the analog circuitry
(AVIN) from the power output stage (PVIN). This
power rails split can be utilized to reduce the internal
power dissipation. And this also permits G2995 to pro-
vide a termination solution for the next generation of
DDR-SDRAM (DDR II).
RT
MENORY
RS
CHIPSET
VREF
Figure 1. SSTL-Termination Scheme
AVIN, PVIN
AVIN and PVIN are two independent input supply pins
for the G2995. AVIN is used to supply all the internal
analog circuits. PVIN is only used to supply the output
stage to create the regulated VTT. To keep the regula-
tion successfully, AVIN should be equal to or larger
than PVIN. Using a higher PVIN voltage will produce a
larger sourcing capability from VTT. But the internal
power loss will also increase and then the heat in-
creases. If the junction temperature exceeds the
thermal shutdown threshold than the G2995 will enter
the shutdown state, where VTT is tri-state and VREF re-
mains active.
Series Stub Termination Logic (SSTL) was created to
improve signal integrity of the data transmission
across the memory bus. This termination scheme is
essential to prevent data error from signal reflections
while transmitting at high frequencies encountered
with DDR-SDRAM. The most common form of termi-
nation is Class II single parallel termination. This in-
volves one RS series resistor from the chipset to the
memory and one RT termination resistor, both 25Ω
typically. The resistors can be changed to scale the
current requirements from the G2995. This implemen-
tation can be seen below in Figure 1.
For SSTL-2 applications, the AVIN and PVIN can be
short together at 2.5V to minimize the PCB complexity
and to reduce the bypassing capacitors for the two
supply pins separately.
TEL: 886-3-5788833
http://www.gmt.com.tw
Ver: 1.7
May 10, 2005
7
GMT [ GLOBAL MIXED-MODE TECHNOLOGY INC ]
