Global Mixed-mode Technology Inc.
Application Information
DIFFSENSE: SOURCE ONLY
FROM TERMPWR
REF
1.3V
1.3V
±0.1V
SOURCE 5 to 15mA
SOURCE/SINK REGULATOR
REF
1.75V
REG1
1.75V
±50mV
50 mA SOURCE/SINK
475 1%
DIFFSENSE
G261
TERMPWR
1µF
to DIFFSENS pin
L1-
4.7µF
121 1%
REG2
SOURCE/SINK REGULATOR
PGND
REF
0.75V
0.75V
±50mV
50 mA SOURCE/SINK
475 1%
4.7µF
L1+
475 1%
L27-
121 1%
475 1%
L27+
Figure 1. LVD SCSI Discrete Resistor Stack
Table1. Resistor Network v.s Standard
OUTPUTS
107.3
Ω
Diff
112.9mV Diff Bias
237
Ω
Common Mode
1.25V Common Mode
SPECIFICATION
100
Ω
to 110
Ω
100mV to 125mV
100
Ω
to 300
Ω
1.2V to 1.30V
Application Note:
The resistor network, along with the 1.75V and 0.75V references will give the correct dif-
ferential impedance, bias voltage, common mode impedance and common mode voltage as show in Table
1.
Layout guideline:
1. For stable operation, the 1µF capacitor on TERMPWR pin and 4.7µF capacitors on REG1 and REG2
pins must be placed within 0.25 inch of their respective pins.
2. The PCB trace length form Lx- and Lx+ to the connector pins (all 27pairs) must be of equal length, in or-
der to minimize the signal skew among these pairs. In addition, these traces must be as short as possible,
in order to minimize capacitance.
Ver 3.2
Dec 13, 2004
TEL: 886-3-5788833
http://www.gmt.com.tw
3
GMT [ GLOBAL MIXED-MODE TECHNOLOGY INC ]
