1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin #
Name
Type
Description
1
2
SDO0VCC
SDO0VEE
NC
Power
Ground
—
Power supply for channel 0 path output.
Ground for channel 0 path output.
No connect.
3, 4
Input Digital LVTTL/LVCMOS-compliant input.
Rate Select Input for the Ch1 Signal Path.
Digital
Input
5
RS1
See Section 3.1 Multirate CDR Functionality for more details.
6, 7
SDI1, SDI1
Input
High-speed input for the channel 1 signal path.
SFP+-compliant active-high digital output. Open-collector Loss-Of-Signal indicator for
the channel 1 signal path. Requires an external pull-up resistor.
Digital
Output
When Ch1LOS is LOW, a valid channel 1 input signal has been detected.
When Ch1LOS is high-impedance, a valid channel 1 input signal has not been detected.
Configurable as LVTTL/LVCMOS-compliant output.
8
Ch1LOS
9
Ch1LF
Ch1VCOVEE
Ch1VCOFILT
Ch1VEE
Passive
Ground
Passive
Ground
Power
Loop filter capacitor connection for the channel 1 signal path.
Ground for the channel 1 signal path VCO.
10
11
12
13
Filter for the channel 1 signal path VCO supply.
Ground for the channel 1 signal path and output.
Power supply for the channel 1 signal path and output.
Ch1VCC
SDO1,
SDO1
14, 15
Output
High-speed differential output for the channel 1 signal path.
Digital active-low LVTTL/LVCMOS-compliant Schmitt-trigger input.
Device reset control pin.
Digital
Input
16
RESET
Includes an internal pull-down resistor to hold the device in a reset state during
power-up, should this pin be externally disconnected.
17
18
Ch0VCC
Ch0VEE
Power
Ground
Input
Power supply for the channel 0 signal path.
Ground for the channel 0 signal path.
19, 20
21
SDI0, SDI0
Ch0VCOFILT
Ch0VCOVEE
Ch0LF
High-speed input for the channel 0 signal path.
Filter for the channel 0 signal path VCO supply.
Ground for the channel 0 signal path VCO.
Loop filter capacitor connection for the Ch0 signal path.
Connect to GND.
Passive
Ground
Passive
Ground
22
23
24
GND
Digital
Input/
Output
Digital active-high serial data signal for the host interface.
Bi-directional, I2C-compliant, open-drain driver/receiver.
25
26
SDA
SCL
Digital
Input
Digital active-high clock input signal for the serial host interface.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
6 of 74
Proprietary & Confidential
55972 - 0
March 2012
GENNUM [ GENNUM CORPORATION ]
