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GS9092ACNE3 参数 Datasheet PDF下载

GS9092ACNE3图片预览
型号: GS9092ACNE3
PDF下载: 下载PDF文件 查看货源
内容描述: GenLINX III 270MB / s的串行器的SDI和DVB -ASI [GenLINX III 270Mb/s Serializer for SDI and DVB-ASI]
分类和应用:
文件页数/大小: 63 页 / 1254 K
品牌: GENNUM [ GENNUM CORPORATION ]
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GS9092A GenLINX® III 270Mb/s Serializer for SDI and DVB-ASI
Key Features
SMPTE 259M-C compliant scrambling and NRZI to NRZ
encoding (with bypass)
DVB-ASI sync word insertion and 8b/10b encoding
Integrated Cable Driver
Integrated line-based FIFO for data alignment/delay,
clock phase interchange, DVB-ASI data packet
insertion, and ancillary data packet insertion
User selectable additional processing features
including:
ANC data checksum, and line number calculation
and insertion
TRS and EDH packet generation and insertion
illegal code remapping
Enhanced Gennum Serial Peripheral Interface (GSPI)
JTAG test interface
+1.8V internal cable driver and core power supply
Optional +1.8V or +3.3V digital I/O power supply
Small footprint (8mm x 8mm)
Low power operation (typically 200mW)
Pb-free and RoHS compliant
Description
The GS9092A is a 270Mb/s serializer with an internal FIFO
and an integrated cable driver. It contains all the necessary
blocks to realize a transmit solution for SD-SDI and
DVB-ASI applications.
In addition to serializing the input data stream, the
GS9092A performs NRZI-to-NRZ encoding and scrambling
as per SMPTE 259M-C when operating in SMPTE mode.
When operating in DVB-ASI mode, the device will insert
K28.5 sync characters and 8b/10b encode the data prior to
serialization.
Parallel data inputs are provided for 10-bit multiplexed
formats at SD signal rates. A 27MHz parallel clock input
signal is also required.
The integrated cable driver features an adjustable signal
swing and common mode operating point offering fully
compliant SMPTE 259M-C cable driver connectivity.
The GS9092A includes a range of data processing functions
such as automatic standards detection and EDH support.
The device can also insert TRS signals, re-map illegal code
words, and generate and insert SMPTE 352M payload
identifier packets. All processing features are optional and
may be enabled/disabled via external control pin(s) and/or
host interface programming.
The GS9092A also incorporates a video line-based FIFO.
This FIFO may be used in four user-selectable modes to
carry out tasks such as data delay, clock phase interchange,
MPEG packet insertion and clock rate interchange, and
ancillary data packet insertion.
The device may also be used as a low-latency
parallel-to-serial converter where the SMPTE scrambling
block will be the only processing feature enabled.
The GS9092A is Pb-free, and the encapsulation compound
does not contain halogenated flame retardant (RoHS
compliant).
Applications
SMPTE 259M-C Serial Digital Interfaces
DVB-ASI Serial Digital Interfaces
GS9092A GenLINX® III 270Mb/s Serializer for SDI and
DVB-ASI
Data Sheet
34715 - 4
May 2010
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