GS9092 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
16
Name
CS_TMS
Timing
Synchronous
with
SCLK_TCK
Type
Input
Description
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Chip Select / Test Mode Select
Host Mode (JTAG/HOST = LOW):
CS/TMS operates as the host interface chip select, CS, and is active
LOW.
JTAG Test Mode (JTAG/HOST = HIGH):
CS/TMS operates as the JTAG test mode select, TMS, and is active
HIGH.
NOTE: If this pin is unused it should be pulled up to VCC_IO.
17
SCLK_TCK
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Clock / Test Clock. All JTAG / Host Interface address and
data is shifted into / out of the device synchronously with this clock.
Host Mode (JTAG/HOST = LOW):
SCLK_TCK operates as the host interface serial data clock, SCLK.
JTAG Test Mode (JTAG/HOST = HIGH):
SCLK_TCK operates as the JTAG test clock, TCK.
NOTE: If this pin is unused it should be pulled up to VCC_IO.
18, 48
CORE_GND
Non
Synchronous
Input
Power
Output
Ground connection for digital logic blocks. Connect to GND.
19
SDOUT_TDO
Synchronous
with
SCLK_TCK
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Output / Test Data Output
Host Mode (JTAG/HOST = LOW):
SDOUT_TDO operates as the host interface serial output, SDOUT,
used to read status and configuration information from the internal
registers of the device.
JTAG Test Mode (JTAG/HOST = HIGH):
SDOUT_TDO operates as the JTAG test data output, TDO.
20
SDIN_TDI
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Serial Data Input / Test Data Input
Host Mode (JTAG/HOST = LOW):
SDIN_TDI operates as the host interface serial input, SDIN, used to
write address and configuration information to the internal registers of
the device.
JTAG Test Mode (JTAG/HOST = HIGH):
SDIN_TDI operates as the JTAG test data input, TDI.
NOTE: If this pin is unused it should be pulled up to VCC_IO.
21, 29, 43
IO_VDD
Non
Synchronous
Input
Power
Power supply for digital I/O.
For a 3.3V tolerant I/O, connect pins to either +1.8V DC or +3.3V DC.
For a 5V tolerant I/O, connect pins to a +3.3V DC.
NOTE: For power sequencing requirements please see
22, 27
RSV
–
–
Reserved. Do Not Connect.
28202 - 2
September 2005
8 of 58
GENNUM [ GENNUM CORPORATION ]
