1.2 Phase Detector
The phase detector compares the phase of the PLL clock
with the phase of the incoming data signal and generates
error correcting timing pulses. The phase detector design
provides a linear transfer function between the input phase
and output timing pulses maximizing the input jitter
tolerance of the PLL.
1.3 Charge Pump
The charge pump takes the phase detector output timing
pulses and creates a charge packet that is proportional to
the system phase error. A unique differential charge pump
design ensures that the output phase does not drift when
data transitions are sparse. This makes the GS9035C ideal
for SMPTE 259M applications where pathological signals
have data transition densities of 0.05.
1.4 Loop Filter
The VCO frequency starts at point A and sweeps up
attempting to lock. If lock is not established during the up
sweep, the VCO is then swept down. The system is
designed such that the probability of locking within one
cycle period is greater than 0.999. If the system does not
lock within one cycle period, it will attempt to lock in the
subsequent cycle. In manual mode, the divider modulus is
fixed for all cycles. In auto mode, each subsequent cycle is
based on a different divider moduli as determined by the
internal 2-bit counter.
The average sweep time, t
swp
, is determined by the loop
filter component, C
LF1
, and the charge pump current,
Ι
CP
:
GS9035C
t
swp
=
4
C
LF1
3
Ι
LF1
[seconds]
The loop filter integrates the charge pump packets and
produces a VCO control voltage. The loop filter is
comprised of three external components which are
connected to pins LF+, LFS, and LF-. The loop filter design
is fully differential giving the GS9035C increased immunity
to PCB board noise.
The loop filter components are critical in determining the
loop bandwidth and damping of the PLL. Choosing these
component values is discussed in detail in the PLL Design
Guidelines section. Recommended values for SMPTE 259M
applications are shown in the Typical Application Circuit
diagram.
2. FREQUENCY ACQUISITION
The nominal sweep time is approximately 121µs when
C
LF1
= 15nF and
Ι
CP
= 165µA (R
VCO
= 365Ω).
An internal system clock determines t
sys
(see
section 7,
Logic Circuit).
3. LOGIC CIRCUIT
The GS9035C is controlled by a finite state logic circuit which
is clocked by an asynchronous system clock. That is, the
system clock is completely independent of the incoming data
rate. The system clock runs at low frequencies, relative to the
incoming data rate, and thus reduces interference to the PLL.
The period of the system clock is set by the COSC capacitor
and is
t
sys
= 9.6 x 10 x COSC
4
[seconds]
The core PLL is able to lock if the incoming data rate and
the PLL clock frequency are within the PLL capture range
(which is slightly larger than the loop bandwidth). To assist
the PLL to lock to data rates outside of the capture range,
the GS9035C uses a frequency acquisition circuit.
The frequency acquisition circuit sweeps the VCO control
voltage such that the VCO frequency changes from -10% to
+10% of the center frequency. Figure 11 shows a typical
sweep waveform.
t
swp
t
sys
The recommended value for t
sys
is 450µs (COSC = 4.7nF).
4. AUTO/MANUAL DATA RATE SELECT
The GS9035C can operate in either auto or manual data
rate select mode. The mode of operation is selected by a
single input pin (AUTO/MAN).
4.1 Auto Mode (AUTO/MAN = 1)
V
LF
In auto mode, the GS9035C uses a 2-bit counter to
automatically cycle through four (SMPTE=1) or two
(SMPTE=0) different divider moduli as it attempts to acquire
lock. In this mode, the SS[1:0] pins are outputs and indicate
the current value of the divider moduli according to Table 2.
Note that for SMPTE = 0 and divider moduli of 2 and 4, the
PLL can correctly lock for two values of SS[1:0].
A
T
cycle
T
cycle
= t
swp
+ t
sys
Fig. 11 Typical Sweep Form
7 of 14
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